The present invention relates generally to rail-to-rail operational amplifiers, and more particularly to improved circuitry for avoiding excess bias current in circuitry which generates tail currents for opposite-conductivity pairs of differentially coupled input transistors when the common mode input voltage is at a high level.
U.S. Pat. No. 5,311,145, issued May 10, 1984 entitled “Combination Driver-Summing Circuit for Rail-to-Rail Differential Amplifier” by Huijsing et al. is believed to be generally indicative of the closest prior art. A “rail-to-rail” operational amplifier is one which has the capability of operating with its common mode input voltage having a value anywhere between the upper and lower power supply voltage rails. In order to achieve a rail-to-rail common-mode input voltage range of an operational amplifier without the use of a charge pump, two pairs of opposite-conductivity inserted after noise input transistors are needed, namely a pair of a N-channel input transistors for operation with the common mode input voltage near the upper power supply voltage and a pair of P-channel input transistors for operation with the common mode input voltage near the lower power supply voltage. The circuit shown in “Prior Art” FIG. 1, which is similar to circuitry in the above-mentioned Huijsing et al. patent, is typically used in order to control the separate tail currents for the N-channel pair of input transistors and the P-channel pair of input transistors so as to maintain their composite transconductance gm at a relatively constant value. This is desirable in order to achieve a relatively constant bandwidth, phase margin, and noise level of the operational amplifier over its common mode input range.
Referring to “Prior Art” FIG. 1, rail-to-rail operational amplifier 1 includes an input stage 2 which includes two pairs of differentially coupled opposite-conductivity input transistors and circuitry for generating their tail currents. The outputs of input stage 2 are coupled to inputs of a conventional folded cascode stage 3. The output of folded cascode stage 3 can be coupled to the input of a conventional class AB output stage 4. More specifically, input stage 2 includes a first differentially coupled pair of P-channel input transistors Q1 and Q2 having their sources connected by conductor 8 to receive a first tail current I1 and also includes a second differentially coupled pair of N-channel input transistors Q3 and Q4 having their sources connected by conductor 5 to receive a second tail current I2. A differential input voltage Vin+-Vin− is coupled between the gate electrodes of P-channel input transistors Q1 and Q2 and also is coupled between the gate electrodes of N-channel input transistors Q2 and Q4. The drains of input transistors Q1-Q4 are coupled to corresponding input terminals of folded cascode stage 3. The rest of the circuitry shown in input stage 2 produces the two tail currents I1 and I2.
A reference current IR is generated in transistor Q8 and flows through cascode transistor Q7, conductor 15, and current mirror control transistor Q9. This causes a corresponding current to flow through current mirror output transistor Q12 and cascode transistor Q13 into the sources of P-channel input transistors Q1 and Q2 as their tail current I1 if they are turned on as a result of the common mode input voltage VCM being less than Vref2. If VCM is greater than Vref2, then current steering transistor Q14 “steers” the current IP from cascode transistor Q13 into cascode transistor Q15 and current mirror output transistor Q16. The current IP therefore is mirrored by means of current mirror output transistor Q11 and flows through cascode transistor Q10 to produce the tail current I2 in conductor 5 for N-channel input transistors Q3 and Q4.
The bias circuitry of input stage 2 in FIG. 1 operates to control tail currents I1 and I2 of the differential input stage including transistors Q1-4 so as to maintain the transconductance gm relatively constant over the entire common mode input voltage range from ground to VDD. When the common mode input voltage VCM is less than Vref2, the current through transistor Q13 is equal to the P-channel tail current I1, and the current IP is zero. When the common-mode input voltage VCM is high enough to exceed Vref2, the P-channel input transistors Q1 and Q2 are turned off and the resulting current IP through transistor Q13 becomes the current which is mirrored to provide an equal value of the N-channel tail current I2, because current mirror transistors Q16 and Q11 typically are matched transistors. Thus, the current IP flowing to ground through transistors Q14, Q15 and Q16 plus the resulting-channel tail current I2 flowing to ground when VCM is less than Vref2 results in roughly twice as much power being dissipated as when VCM is greater than Vref2.
Thus, the bias circuitry in Prior Art FIG. 1 which provides the tail currents I1 and I2 consumes about twice the amount of current (and power) when N-channel input transistors Q3 and Q4 are active than when P-channel input transistors Q1 and Q2 are active. Although the technique for generating tail current in FIG. 1 is very common, it is wasteful of current (and power). This is because if the circuitry of FIG. 1 is designed to optimize the speed-to-current ratio, the tail currents I1 and I2 are minimal compared to the rest of the current in the operational amplifier circuit. However, if the circuit of FIG. 1 is designed to optimize the noise-to-current ratio (or noise-to-power ratio), then there typically will be relatively large input tail currents, which would result in very fast amplifier operation, making it necessary to use frequency compensation techniques to reduce the speed to a normal level, since the only way to reduce the total quiescent current of the operational amplifier is to reduce the speed. That is, if the circuit of FIG. 1 is being designed to minimize the noise for a given total quiescent current, the tail current typically will be a much more significant portion of the total quiescent current for the operational amplifier, and the large value of IP that is required to generate the large value of N-channel tail current I2 becomes problematic.
Thus, there is an unmet need for rail-to-rail differential input amplifier circuitry which avoids wasting bias current when a particular pair of differentially coupled input transistors is turned off.
There also is an unmet need for rail-to-rail operational amplifier circuitry which avoids wasting bias current when a particular pair of differentially coupled input transistors is turned off in the case wherein the operational amplifier circuitry is being designed for a low noise-to-current ratio.